Mechanical stress is one of the major factors in current design and manufacture of Very Large Scale Integrated (VLSI) devices. Mechanical stress in deep sub-micron silicon (Si) technologies can drastically alter carrier mobility (e.g., approximately 25% dependent on device geometry). This affects the device performance. Current in-line production stress metrology is conducted only at a wafer monitor level. For design purposes, the stress state in active device regions has been inferred from electrical data. The available stress measurement techniques such as micro-Raman spectroscopy, Nano Beam Diffraction (NBD), Converging Electron Beam Diffraction (CEBD) either do not have required resolution or they require complex data interpretation or destructive. Therefore when devices are scaled down, these methods can not be used for measuring local stress levels present in the device. In collaboration with the IBM, during my internships, we developed a method for measuring mechanical stress in deep sub-micron silicon devices with high spatial resolution using scanning Kelvin probe force microscopy and differential surface photo-voltage (DSPV) techniques.